1. Field of the Invention
The present invention relates to a SiC semiconductor device that is metal-insulator-semiconductor (MIS) field-effect transistor fabricated on a silicon carbide substrate. It particularly relates to a SiC semiconductor device having al optimized impurity diffusion layer and a defined substrate crystal plane orientation.
2. Description of the Prior Art
Silicon carbide has an energy gap that is two to three times larger than that of silicon and a breakdown voltage that is about three times higher. Silicon carbide is being viewed as the substrate material for the next generation of transistors for high-power, high-temperature and high-frequency applications. In particular, considerable expectations are being placed on metal-insulator-semiconductor field-effect transistors (MISFETs) for use as switching devices, since MISFETs are faster than bipolar transistors.
However, when a silicon carbide substrate is used, the interface between the oxide and the silicon carbide has an interface level density that is approximately one magnitude higher than that of a silicon MIS transistor. Thus, there is the problem that an MIS field-effect transistor that uses a silicon carbide substrate has a channel mobility that is approximately one magnitude lower than an MIS field-effect transistor that has a silicon substrate.
To make silicon MIS transistors less susceptible to the effect of the interface between the oxide layer and silicon carbide when electrons are flowing from the source to the drain, an MIS field-effect transistor having a buried channel region is known to exhibit excellent characteristics. However, in the case of an MIS transistor on a silicon carbide substrate, so far the optimization of buried channel region transistors has not been adequate, and have tended to operate as normally on (a state in which there is still a current flow between source and drain even when there is zero gate voltage), making the device difficult to use. Moreover, MIS transistors that are not normalized have poor hot-carrier endurance that results in inadequate punch-through endurance.
A number of inventions have been disclosed for improving the characteristics of buried channel MIS field-effect transistors. U.S. Pat. No. 5,864,157, for example, describes a double-gate flash memory that uses a P-type lower gate and an N-impurity in a buried channel region. However, since this only relates to a double-gate flash memory, it is different from the structure of the present invention. Moreover, the disclosure does not touch either on the concentration of the P-type polycrystalline silicon electrode and the impurity concentration of the buried channel region, or on the relationship of the depth of the source and drain regions and the depth of the channel region.
JP-A Hei 8-186179 describes an N-channel transistor having a lightly doped drain (LDD) structure with a P-gate and an N-doped buried channel region. However, the disclosure does not describe either the concentration of the P-type polycrystalline silicon electrode, or the relationship between the depths of the source and drain regions and the depth of the channel region. Similarly, JP-A Hei 7-131016 describes an MIS field-effect transistor characterized in that the channel formation face is parallel to the (11-20) surface of the hexagonal silicon carbide single-crystal substrate. However, the disclosure does not describe a buried channel region MIS field-effect transistor that uses a P-type gate.
An object of the present invention is to provide a SiC semiconductor device that is a buried channel region MIS transistor that is not put into a normally on state by optimization of the buried channel region type MIS transistor structure or silicon carbide No substrate crystal plane orientation, and has high hot-carrier endurance, high punch-through endurance and high channel mobility.
To attain the above object, the present invention provides a SiC semiconductor device comprising a semiconductor substrate having a P-type silicon carbide region, a gate insulation layer formed on the silicon carbide region, a P-type gate electrode formed on the gate insulation layer, an N-type impurity region having an impurity concentration sufficient to form a buried channel region in a semiconductor layer on a lower surface of the gate insulation layer, and source and drain regions comprised of N-type impurity regions formed adjacent to the gate insulation layer and gate electrode.
The invention also comprises the above device in which, in order to optimize the depth of the buried channel region and achieve high mobility, the ratio (Lbc/Xj) is not less than 0.2 and not more than 1.0, where the Lbc is the depth from the interface between the gate insulation layer and the silicon carbide to the buried channel region, and the Xj is the depth from the interface between the gate insulation layer and the silicon carbide to the source and drain region junction.
The invention also comprises the device described above in which the gate electrode is comprised of polycrystalline silicon in which boron or aluminum is diffused at a concentration within a range 1xc3x971016 cmxe2x88x923 to 1xc3x971021 cmxe2x88x923.
The invention also comprises the above device in which the buried channel region contains a diffusion of nitrogen, phosphorus, or arsenic at a maximum concentration that is from 5xc3x971015 cmxe2x88x923 to 1xc3x971018 cmxe2x88x923.
The invention also comprises the above device in which the gate includes a silicide layer of a refractory metal.
The invention also comprises the above device in which the refractory metal is tungsten, molybdenum or titanium.
The invention also comprises the above device in which, between the buried channel region and the source and drain regions, there is a region having an impurity concentration that is not lower than a maximum impurity concentration of the impurity layer region used to form the buried channel region and not higher than an impurity concentration of the source or drain regions.
The invention also comprises the above device in which there is included, between the buried channel region and the source and drain regions, a diffusion layer of nitrogen, phosphorus or arsenic at a maximum concentration that is from 5xc3x971016 cmxe2x88x923 to 5xc3x971019 cmxe2x88x923.
The invention also comprises the above device in which, located adjacently under the buried channel formation region is a P-type impurity diffusion region having an impurity concentration that is higher than an impurity concentration of the semiconductor substrate.
The invention also comprises the above device that has a high-concentration P-type impurity diffusion region located adjacently under the buried channel region that includes an aluminum or boron diffusion layer having a maximum impurity concentration of 1xc3x971017 cmxe2x88x923 to 1xc3x971019 cmxe2x88x923.
The invention also comprises the above device that is formed on a (11-20) surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal in order to improve the channel mobility.
The invention also comprises the above device that has a lateral resurf or lateral DMOS type MOSFET structure.
The invention also comprises the above device that has a DMOS type MOSFET structure.
The invention also comprises the above device in which the gate electrode is formed of aluminum or an alloy that contains aluminum.
Further features of the invention, its nature and various advantages will be more apparent from the following detailed description which is to be read in conjunction with the accompanying drawings.